Power Reduction and Power - Delay Tradeo s using

An eecient technique to reduce the switching activity in a technology mapped CMOS combi-national circuit based on local logic transformations is presented. The transformations consist of adding redundant connections or gates so as to reduce the switching activity. Simple and eecient procedures, based on logic implication, for identifying the sources and targets of the redundant connections are described. Additionally, procedures that permit the designer to tradeoo power and delay after the transformations are presented. Results of experiments on both the MCNC benchmark circuits and the circuits of a PowerPC microprocessor chip are given. The results indicate that signiicant power reduction of a CMOS combinational circuit can be achieved with very low area overhead , delay penalty and computational cost.